[SPARC] Prevent RESTORE from sourcing from %o7 in call delay slots

llvm/lib/Target/Sparc/DelaySlotFiller.cpp

@@ -303,15 +303,20 @@ void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI,
                                 SmallSet<unsigned, 32>& RegDefs,
                                 SmallSet<unsigned, 32>& RegUses)
 {
-  // Call defines o7, which is visible to the instruction in delay slot.
-  RegDefs.insert(SP::O7);
-
+  // Regular calls define o7, which is visible to the instruction in delay slot.
+  // On the other hand, tail calls preserve it.
   switch(MI->getOpcode()) {
   default: llvm_unreachable("Unknown opcode.");
   case SP::CALL:
+    RegDefs.insert(SP::O7);
+    break;
+  case SP::TAIL_CALL:
     break;
   case SP::CALLrr:
   case SP::CALLri:
+    RegDefs.insert(SP::O7);
+    [[fallthrough]];
+  case SP::TAIL_CALLri:
     assert(MI->getNumOperands() >= 2);
     const MachineOperand &Reg = MI->getOperand(0);
     assert(Reg.isReg() && "CALL first operand is not a register.");
@@ -390,10 +395,10 @@ bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
   return true;
 }
 
-static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI,
+static bool combineRestoreADD(MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator RestoreMI,
                               MachineBasicBlock::iterator AddMI,
-                              const TargetInstrInfo *TII)
-{
+                              const TargetInstrInfo *TII) {
   // Before:  add  <op0>, <op1>, %i[0-7]
   //          restore %g0, %g0, %i[0-7]
   //
@@ -403,6 +408,20 @@ static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI,
   if (reg < SP::I0 || reg > SP::I7)
     return false;
 
+  // Check whether it uses %o7 as its source and the corresponding branch
+  // instruction is a call.
+  MachineBasicBlock::iterator LastInst = MBB.getFirstTerminator();
+  bool IsCall = LastInst != MBB.end() && LastInst->isCall();
+
+  if (IsCall && AddMI->getOpcode() == SP::ADDrr &&
+      (AddMI->getOperand(1).getReg() == SP::O7 ||
+       AddMI->getOperand(2).getReg() == SP::O7))
+    return false;
+
+  if (IsCall && AddMI->getOpcode() == SP::ADDri &&
+      AddMI->getOperand(1).getReg() == SP::O7)
+    return false;
+
   // Erase RESTORE.
   RestoreMI->eraseFromParent();
 
@@ -417,10 +436,10 @@ static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI,
   return true;
 }
 
-static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI,
+static bool combineRestoreOR(MachineBasicBlock &MBB,
+                             MachineBasicBlock::iterator RestoreMI,
                              MachineBasicBlock::iterator OrMI,
-                             const TargetInstrInfo *TII)
-{
+                             const TargetInstrInfo *TII) {
   // Before:  or  <op0>, <op1>, %i[0-7]
   //          restore %g0, %g0, %i[0-7]
   //    and <op0> or <op1> is zero,
@@ -442,6 +461,20 @@ static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI,
       && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
     return false;
 
+  // Check whether it uses %o7 as its source and the corresponding branch
+  // instruction is a call.
+  MachineBasicBlock::iterator LastInst = MBB.getFirstTerminator();
+  bool IsCall = LastInst != MBB.end() && LastInst->isCall();
+
+  if (IsCall && OrMI->getOpcode() == SP::ORrr &&
+      (OrMI->getOperand(1).getReg() == SP::O7 ||
+       OrMI->getOperand(2).getReg() == SP::O7))
+    return false;
+
+  if (IsCall && OrMI->getOpcode() == SP::ORrr &&
+      OrMI->getOperand(1).getReg() == SP::O7)
+    return false;
+
   // Erase RESTORE.
   RestoreMI->eraseFromParent();
 
@@ -520,9 +553,13 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
   switch (PrevInst->getOpcode()) {
   default: break;
   case SP::ADDrr:
-  case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break;
+  case SP::ADDri:
+    return combineRestoreADD(MBB, MBBI, PrevInst, TII);
+    break;
   case SP::ORrr:
-  case SP::ORri:  return combineRestoreOR(MBBI, PrevInst, TII); break;
+  case SP::ORri:
+    return combineRestoreOR(MBB, MBBI, PrevInst, TII);
+    break;
   case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break;
   }
   // It cannot combine with the previous instruction.

llvm/lib/Target/Sparc/SparcInstrInfo.td

@@ -1588,8 +1588,8 @@ let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
 //===----------------------------------------------------------------------===//
 // Instructions for tail calls.
 //===----------------------------------------------------------------------===//
-let isCodeGenOnly = 1, isReturn = 1,  hasDelaySlot = 1,
-    isTerminator = 1, isBarrier = 1 in {
+let isCodeGenOnly = 1, isReturn = 1, hasDelaySlot = 1, isTerminator = 1,
+    isBarrier = 1, isCall = 1 in {
   def TAIL_CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
                          "call $disp",
                          [(tailcall tglobaladdr:$disp)]> {
@@ -1602,8 +1602,8 @@ let isCodeGenOnly = 1, isReturn = 1,  hasDelaySlot = 1,
 def : Pat<(tailcall (iPTR texternalsym:$dst)),
           (TAIL_CALL texternalsym:$dst)>;
 
-let isCodeGenOnly = 1, isReturn = 1,  hasDelaySlot = 1,  isTerminator = 1,
-    isBarrier = 1, rd = 0 in {
+let isCodeGenOnly = 1, isReturn = 1, hasDelaySlot = 1, isTerminator = 1,
+    isBarrier = 1, isCall = 1, rd = 0 in {
   def TAIL_CALLri : F3_2<2, 0b111000,
                          (outs), (ins (MEMri $rs1, $simm13):$addr, variable_ops),
                          "jmp $addr",