[llvm][RISCV] Support Zvfofp8min llvm intrinsics and codegen

llvm/include/llvm/IR/IntrinsicsRISCV.td

@@ -1958,6 +1958,26 @@ let TargetPrefix = "riscv" in {
 let TargetPrefix = "riscv" in
 def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
 
+
+//===----------------------------------------------------------------------===//
+// Zvfofp8min - OFP8 conversion extension
+// The Zvfofp8min extension provides basic support for the two 8-bit
+// floating-point formats defined in the Open Compute Project OFP8
+// specification, OFP8 E4M3 and OFP8 E5M2.
+let TargetPrefix = "riscv" in {
+  // OFP8 to BF16 conversion instructions
+  defm vfwcvt_f_f_v_alt : RISCVConversion;
+  // BF16 to OFP8 conversion instructions
+  defm vfncvt_sat_f_f_w : RISCVConversionRoundingMode;
+  defm vfncvt_f_f_w_alt : RISCVConversionRoundingMode;
+  defm vfncvt_sat_f_f_w_alt : RISCVConversionRoundingMode;
+  // FP32 to OFP8 conversion instructions
+  defm vfncvt_f_f_q : RISCVConversionRoundingMode;
+  defm vfncvt_f_f_q_alt : RISCVConversionRoundingMode;
+  defm vfncvt_sat_f_f_q : RISCVConversionRoundingMode;
+  defm vfncvt_sat_f_f_q_alt : RISCVConversionRoundingMode;
+} // TargetPrefix = "riscv"
+
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 include "llvm/IR/IntrinsicsRISCVXTHead.td"

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

@@ -216,11 +216,13 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
                                    const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
   // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx,
-  // altfmt=1 without zvfbfa extension, or non-zero in bits 9 and above.
+  // altfmt=1 without zvfbfa or zvfofp8min extension, or non-zero in bits 9 and
+  // above.
   if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED ||
       RISCVVType::getSEW(Imm) > 64 ||
       (RISCVVType::isAltFmt(Imm) &&
        !(STI.hasFeature(RISCV::FeatureStdExtZvfbfa) ||
+         STI.hasFeature(RISCV::FeatureStdExtZvfofp8min) ||
          STI.hasFeature(RISCV::FeatureVendorXSfvfbfexp16e))) ||
       (Imm >> 9) != 0) {
     O << formatImm(Imm);

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

@@ -5851,8 +5851,9 @@ multiclass VPatConversionWF_VI<string intrinsic, string instruction,
 }
 
 multiclass VPatConversionWF_VF<string intrinsic, string instruction,
+                               list<VTypeInfoToWide> wlist = AllWidenableFloatVectors,
                                bit isSEWAware = 0> {
-  foreach fvtiToFWti = AllWidenableFloatVectors in {
+  foreach fvtiToFWti = wlist in {
     defvar fvti = fvtiToFWti.Vti;
     defvar fwti = fvtiToFWti.Wti;
     // Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
@@ -7177,6 +7178,7 @@ defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU",
 defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X",
                            isSEWAware=1>;
 defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F",
+                           wlist=AllWidenableFloatVectors,
                            isSEWAware=1>;
 
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td

@@ -24,3 +24,134 @@ let Predicates = [HasStdExtZvfofp8min], Constraints = "@earlyclobber $vd",
   defm VFNCVT_F_F_Q : VNCVTF_FV_VS2<"vfncvt.f.f.q", 0b010010, 0b11001>;
   defm VFNCVT_SAT_F_F_Q : VNCVTF_FV_VS2<"vfncvt.sat.f.f.q", 0b010010, 0b11011>;
 }
+
+//===----------------------------------------------------------------------===//
+// Pseudo instructions
+//===----------------------------------------------------------------------===//
+defvar MxListQ = [V_MF8, V_MF4, V_MF2, V_M1, V_M2];
+
+defset list<VTypeInfoToWide> AllWidenableIntToBFloatVectors = {
+  def : VTypeInfoToWide<VI8MF8, VBF16MF4>;
+  def : VTypeInfoToWide<VI8MF4, VBF16MF2>;
+  def : VTypeInfoToWide<VI8MF2, VBF16M1>;
+  def : VTypeInfoToWide<VI8M1, VBF16M2>;
+  def : VTypeInfoToWide<VI8M2, VBF16M4>;
+  def : VTypeInfoToWide<VI8M4, VBF16M8>;
+}
+
+defset list<VTypeInfoToWide> AllWidenableInt8ToFloat32Vectors = {
+  def : VTypeInfoToWide<VI8MF8, VF32MF2>;
+  def : VTypeInfoToWide<VI8MF4, VF32M1>;
+  def : VTypeInfoToWide<VI8MF2, VF32M2>;
+  def : VTypeInfoToWide<VI8M1, VF32M4>;
+  def : VTypeInfoToWide<VI8M2, VF32M8>;
+}
+
+class QVRClass<LMULInfo m> {
+  LMULInfo c = !cond(!eq(m, V_MF8): V_MF2,
+                     !eq(m, V_MF4): V_M1,
+                     !eq(m, V_MF2): V_M2,
+                     !eq(m, V_M1): V_M4,
+                     !eq(m, V_M2): V_M8);
+}
+
+multiclass VPseudoVWCVTD_V_NoSched_Zvfofp8min {
+  defvar constraint = "@earlyclobber $rd";
+  foreach m = MxListW in {
+    defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, sew=8,
+                                TargetConstraintType=3>;
+  }
+}
+
+multiclass VPseudoVNCVTD_W_RM_NoSched_Zvfofp8min {
+  defvar constraint = "@earlyclobber $rd";
+  foreach m = MxListW in {
+    defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m,
+                                            constraint, sew=8,
+                                            TargetConstraintType=2>;
+  }
+}
+
+multiclass VPseudoVNCVTD_Q_RM_NoSched_Zvfofp8min {
+  defvar constraint = "@earlyclobber $rd";
+  foreach m = MxListQ in {
+    defm _Q : VPseudoConversionRoundingMode<m.vrclass, QVRClass<m>.c.vrclass, m,
+                                            constraint, sew=8,
+                                            TargetConstraintType=2>;
+  }
+}
+
+let Predicates = [HasStdExtZvfofp8min] in {
+  let AltFmtType = IS_NOT_ALTFMT in
+    defm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V_NoSched_Zvfofp8min;
+  let AltFmtType = IS_ALTFMT in
+    defm PseudoVFWCVTBF16_F_F_ALT : VPseudoVWCVTD_V_NoSched_Zvfofp8min;
+  let mayRaiseFPException = true in {
+    let AltFmtType = IS_NOT_ALTFMT in {
+      defm PseudoVFNCVTBF16_F_F :     VPseudoVNCVTD_W_RM_NoSched_Zvfofp8min;
+      defm PseudoVFNCVTBF16_SAT_F_F : VPseudoVNCVTD_W_RM_NoSched_Zvfofp8min;
+      defm PseudoVFNCVT_F_F :         VPseudoVNCVTD_Q_RM_NoSched_Zvfofp8min;
+      defm PseudoVFNCVT_SAT_F_F :     VPseudoVNCVTD_Q_RM_NoSched_Zvfofp8min;
+    }
+    let AltFmtType = IS_ALTFMT in {
+      defm PseudoVFNCVTBF16_F_F_ALT :     VPseudoVNCVTD_W_RM_NoSched_Zvfofp8min;
+      defm PseudoVFNCVTBF16_SAT_F_F_ALT : VPseudoVNCVTD_W_RM_NoSched_Zvfofp8min;
+      defm PseudoVFNCVT_F_F_ALT :         VPseudoVNCVTD_Q_RM_NoSched_Zvfofp8min;
+      defm PseudoVFNCVT_SAT_F_F_ALT :     VPseudoVNCVTD_Q_RM_NoSched_Zvfofp8min;
+    }
+  }
+}
+
+//===----------------------------------------------------------------------===//
+// Patterns
+//===----------------------------------------------------------------------===//
+multiclass VPatConversionQF_RM<string intrinsic, string instruction,
+                               bit isSEWAware = 0> {
+  foreach fvtiToFWti = AllWidenableInt8ToFloat32Vectors in {
+    defvar fvti = fvtiToFWti.Vti;
+    defvar fwti = fvtiToFWti.Wti;
+    let Predicates = [HasStdExtZvfofp8min] in
+    defm : VPatConversionRoundingMode<intrinsic, instruction, "Q",
+                                      fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
+                                      fvti.LMul, fvti.RegClass, fwti.RegClass,
+                                      isSEWAware>;
+  }
+}
+
+let Predicates = [HasStdExtZvfofp8min] in {
+  // OFP8 to BF16 conversion instructions
+  defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v",
+                             "PseudoVFWCVTBF16_F_F",
+                             wlist=AllWidenableIntToBFloatVectors,
+                             isSEWAware=1>;
+  defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v_alt",
+                             "PseudoVFWCVTBF16_F_F_ALT",
+                             wlist=AllWidenableIntToBFloatVectors,
+                             isSEWAware=1>;
+  // BF16 to OFP8 conversion instructions
+  defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", 
+                                "PseudoVFNCVTBF16_F_F",
+                                wlist=AllWidenableIntToBFloatVectors,
+                                isSEWAware=1>;
+  defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_sat_f_f_w", 
+                                "PseudoVFNCVTBF16_SAT_F_F",
+                                wlist=AllWidenableIntToBFloatVectors,
+                                isSEWAware=1>;
+  defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w_alt", 
+                                "PseudoVFNCVTBF16_F_F_ALT",
+                                wlist=AllWidenableIntToBFloatVectors,
+                                isSEWAware=1>;
+  defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_sat_f_f_w_alt", 
+                                "PseudoVFNCVTBF16_SAT_F_F_ALT",
+                                 wlist=AllWidenableIntToBFloatVectors,
+                                 isSEWAware=1>;
+  // FP32 to OFP8 conversion instructions
+  defm : VPatConversionQF_RM<"int_riscv_vfncvt_f_f_q",
+                             "PseudoVFNCVT_F_F", isSEWAware=1>;
+  defm : VPatConversionQF_RM<"int_riscv_vfncvt_sat_f_f_q",
+                             "PseudoVFNCVT_SAT_F_F", isSEWAware=1>;
+  defm : VPatConversionQF_RM<"int_riscv_vfncvt_f_f_q_alt",
+                             "PseudoVFNCVT_F_F_ALT", isSEWAware=1>;
+  defm : VPatConversionQF_RM<"int_riscv_vfncvt_sat_f_f_q_alt",
+                             "PseudoVFNCVT_SAT_F_F_ALT", isSEWAware=1>;
+}