Sifive 0.6.0 internal release

What's Changed

• [FIRRTL] [CheckCombCycle] Print a cycle while dumping signal names by @uenoku in #2942
• [Scheduling] Add consistency check. by @jopperm in #2953
• [Calyx] Update MultPipeOp and DivPipeOp format to round-trip. by @mikeurbach in #2954
• [Calyx] Add WireLibOp to represent a wire in Calyx's core library. by @mikeurbach in #2956
• [firtool] Apply CLI options to exportPm by @uenoku in #2961
• [FIRRTL] Do not dedup testharness memories by @prithayan in #2968
• [ExportVerilog] Fix an iterator update bug by @uenoku in #2964
• [ExportVerilog] Add a mechanism to control location info emission style by @uenoku in #2952
• [reduce] Add NodeSymbolRemover reduction by @uenoku in #2965
• WIP - Bump llvm. by @mikeurbach in #2969
• Revert "WIP - Bump llvm." by @mikeurbach in #2972
• Bump LLVM to 2d014b72ccb51de9a9627c31667a3edf8cca7616 (#2969) by @mikeurbach in #2973
• [FIRRTL] Omnibus fixes for Grand Central Signal Mappings by @seldridge in #2950
• [FIRRTL] Do not dedup testharness memory irrespective of Prefix by @prithayan in #2977
• Cmdline flags to deal with subcircuit by @darthscsi in #2981
• [FIRRTL] Make GroupID memory attribute unsigned. NFC by @prithayan in #2975
• [FIRRTL][Dedup] Fix MustDedup crash by @youngar in #2983
• [StandardToHandshake] Support external functions by @mortbopet in #2984
• [StandardToHandshake] Fix function type for external FuncOps by @mortbopet in #2987
• Update dialect overview diagram by @jopperm in #2976
• [FIRRTL] Add "_ext" suffix to Memory module and instance name by @prithayan in #2982
• [FIRRTL] Add a memory lowering pass by @prithayan in #2967
• [FIRRTL] Rename LowerMemory to FlattenMemory by @youngar in #2992
• [FIRRTL] Add documentation for AddSeqMemPort annotations by @youngar in #2993
• [FIRRTL] print mem.conf even if there are no memories by @youngar in #2991
• [FIRRTL][ModuleInliner] fix flatten+inline into multiple instance sites, annotation cleanup by @dtzSiFive in #2998
• [FIRRTL] [CheckCombCycles] Improve error message by reconstructing a full cycle by @uenoku in #2970
• [StandardToHandshake] enable reuse by exposing region lowering by @Dinistro in #2986
• [PyCDE] [NFC] Refactoring out the op caching code by @teqdruid in #3006
• [FIRRTL][LowerToHW] Insert extra initialization for async regs by @uenoku in #3000
• [MSFT] Make dynamic instances hierarchical by @teqdruid in #3005
• [PyCDE] [NFC] Rework instance hierarchy by @teqdruid in #3007
• [PyCDE] Teach PlacementDB how to resolve to Instances by @teqdruid in #3008
• [PyCDE] Adds support for rebuilding the instance cache by @teqdruid in #3011
• [Handshake] Make builders more flexible by using ValueRange by @Dinistro in #3013
• [SV] Avoid temporary wires when ReadInOutOp is after use by @nandor in #3009
• [Handshake] Improve handshake builders by @Dinistro in #3014
• [Handshake] Add optional visibility parsing for FuncOp by @Dinistro in #3016
• [FIRRTL] Add InjectDUTHierarchy Pass by @seldridge in #2989
• [Handshake] Add sink materialization for block arguments by @Dinistro in #3022
• [HW] Remove InstanceOp's constaint on the symbol by @youngar in #2994
• [HW] InnerNameRef backed by a symbol by @nandor in #2815
• [HW] Added a helper method to HWModuleOp to insert new outputs by @nandor in #2997
• FIREmitter: give strictconnect same invalid treatment, add test by @dtzSiFive in #3029
• [SV] Added macro.ref to reference macros. by @nandor in #2921
• FIRParser: fix ref invalidation in connectDebugInfo,emitPartialConnect by @dtzSiFive in #3026
• [FIRRTL] check flip orientation in connect operations by @dtzSiFive in #3025
• [FIRRTL] DUT seq mems paths should start from the DUT module. by @richardxia in #3031

New Contributors

• @dtzSiFive made their first contribution in #2998

Full Changelog: sifive/0/5/0...sifive/0/6/0