[SeqToSV] Initialize buried preset registers using XMRs

Author: rwy7

lib/Conversion/SeqToSV/FirRegLowering.cpp

@@ -357,6 +357,8 @@ void FirRegLowering::createRandomInitialization(ImplicitLocOpBuilder &builder) {
 
 void FirRegLowering::createPresetInitialization(ImplicitLocOpBuilder &builder) {
   for (auto &svReg : presetInitRegs) {
+    OpBuilder::InsertionGuard guard(builder);
+
     auto loc = svReg.reg.getLoc();
     auto elemTy = svReg.reg.getType().getElementType();
     auto cst = getOrCreateConstant(loc, svReg.preset.getValue());
@@ -367,7 +369,13 @@ void FirRegLowering::createPresetInitialization(ImplicitLocOpBuilder &builder) {
     else
       rhs = hw::BitcastOp::create(builder, loc, elemTy, cst);
 
-    sv::BPAssignOp::create(builder, loc, svReg.reg, rhs);
+    buildRegConditions(builder, svReg.reg);
+    Value target = svReg.reg;
+    if (svReg.path)
+      target = buildXMRTo(builder, svReg.path, svReg.reg.getLoc(),
+                          svReg.reg.getType());
+
+    sv::BPAssignOp::create(builder, loc, target, rhs);
   }
 }
 

test/Dialect/Seq/firreg.mlir

@@ -1043,3 +1043,29 @@ hw.module @AsyncResetRegUnderIfdef(in %clock : !seq.clock, in %reset : i1, in %v
   // CHECK: }
   hw.output
 }
+
+// Test for registers with "preset".
+
+// CHECK:  hw.hierpath @[[reg_path:.+]] [@PresetRegUnderIfdef::@reg]
+hw.module @PresetRegUnderIfdef(in %clock : !seq.clock, in %value : i1) {
+  %c = hw.constant 0 : i1
+
+  // CHECK: sv.ifdef @MyMacro {
+  // CHECK:   %reg = sv.reg sym @reg : !hw.inout<i1>
+  // CHECK:   %0 = sv.read_inout %reg : !hw.inout<i1>
+  // CHECK:   sv.always posedge %clock {
+  // CHECK:     sv.passign %reg, %value : i1
+  // CHECK:   }
+  // CHECK: }
+  sv.ifdef @MyMacro {
+    %reg = seq.firreg %value clock %clock preset 0: i1
+  }
+
+  // CHECK: sv.initial {
+  // CHECK:   sv.ifdef.procedural @MyMacro {
+  // CHECK:     %0 = sv.xmr.ref @[[reg_path]] : !hw.inout<i1>
+  // CHECK:     sv.bpassign %0, %false : i1
+  // CHECK:   }
+  // CHECK: }
+  hw.output
+}