[SeqToSV] Use XMR to set up async reset of firreg

With inline layers, firregs may now appear under ifdef blocks. This PR
updates the generation of the reset IR to reference a firreg by XMR if
the register is buried under an ifdef.

Author: rwy7

lib/Conversion/SeqToSV/FirRegLowering.cpp

@@ -23,6 +23,13 @@ using llvm::MapVector;
 
 #define DEBUG_TYPE "lower-seq-firreg"
 
+static Value buildXMRTo(OpBuilder &builder, HierPathOp path, Location loc,
+                        Type type) {
+  auto name = path.getSymNameAttr();
+  auto ref = mlir::FlatSymbolRefAttr::get(name);
+  return sv::XMRRefOp::create(builder, loc, type, ref);
+}
+
 /// Immediately before the terminator, if present. Otherwise, the block's end.
 static Block::iterator getBlockEnd(Block *block) {
   if (block->mightHaveTerminator())
@@ -370,13 +377,22 @@ void FirRegLowering::createPresetInitialization(ImplicitLocOpBuilder &builder) {
 void FirRegLowering::createAsyncResetInitialization(
     ImplicitLocOpBuilder &builder) {
   for (auto &reset : asyncResets) {
+    OpBuilder::InsertionGuard guard(builder);
+
     //  if (reset) begin
     //    ..
     //  end
-    sv::IfOp::create(builder, reset.first, [&] {
-      for (auto &reg : reset.second)
-        sv::BPAssignOp::create(builder, reg.reg.getLoc(), reg.reg,
+    sv::IfOp::create(builder, reset.first, [&]() {
+      for (auto &reg : reset.second) {
+        OpBuilder::InsertionGuard guard(builder);
+        buildRegConditions(builder, reg.reg);
+        Value target = reg.reg;
+        if (reg.path)
+          target = buildXMRTo(builder, reg.path, reg.reg.getLoc(),
+                              reg.reg.getType());
+        sv::BPAssignOp::create(builder, reg.reg.getLoc(), target,
                                reg.asyncResetValue);
+      }
     });
   }
 }
@@ -798,13 +814,6 @@ void FirRegLowering::buildRegConditions(OpBuilder &b, sv::RegOp reg) {
   }
 }
 
-static Value buildXMRTo(OpBuilder &builder, HierPathOp path, Location loc,
-                        Type type) {
-  auto name = path.getSymNameAttr();
-  auto ref = mlir::FlatSymbolRefAttr::get(name);
-  return sv::XMRRefOp::create(builder, loc, type, ref);
-}
-
 void FirRegLowering::initialize(OpBuilder &builder, RegLowerInfo reg,
                                 ArrayRef<Value> rands) {
   auto loc = reg.reg.getLoc();

test/Dialect/Seq/firreg.mlir

@@ -1011,3 +1011,35 @@ hw.module @RegUnderIfdefDupName(in %clock : !seq.clock, in %reset : i1, in %valu
   }
   hw.output
 }
+
+// Test for registers with async resets.
+
+// CHECK:  hw.hierpath @[[reg_path:.+]] [@AsyncResetRegUnderIfdef::@reg]
+hw.module @AsyncResetRegUnderIfdef(in %clock : !seq.clock, in %reset : i1, in %value : i1) {
+  %c = hw.constant 0 : i1
+
+  // CHECK: sv.ifdef @MyMacro {
+  // CHECK:   %reg = sv.reg sym @reg : !hw.inout<i1>
+  // CHECK:   %0 = sv.read_inout %reg : !hw.inout<i1>
+  // CHECK:   sv.always posedge %clock, posedge %reset {
+  // CHECK:     sv.if %reset {
+  // CHECK:       sv.passign %reg, %false_0 : i1
+  // CHECK:     } else {
+  // CHECK:       sv.passign %reg, %value : i1
+  // CHECK:     }
+  // CHECK:   }
+  // CHECK: }
+  sv.ifdef @MyMacro {
+    %reg = seq.firreg %value clock %clock reset async %reset, %c : i1
+  }
+
+  // CHECK: sv.initial {
+  // CHECK:   sv.if %reset {
+  // CHECK:     sv.ifdef.procedural @MyMacro {
+  // CHECK:       %0 = sv.xmr.ref @[[reg_path]] : !hw.inout<i1>
+  // CHECK:       sv.bpassign %0, %false_0 : i1
+  // CHECK:     }
+  // CHECK:   }
+  // CHECK: }
+  hw.output
+}