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7 changes: 6 additions & 1 deletion port/wch/ch32v/src/cpus/main.zig
Original file line number Diff line number Diff line change
Expand Up @@ -253,7 +253,6 @@ pub const startup_logic = struct {
},
}

// Enable interrupts.
// Set mtvec.base to (vector_table_address - 4) >> 2 so that interrupt N
// jumps to the correct handler regardless of any padding between _reset_vector
// and vector_table.
Expand All @@ -263,10 +262,16 @@ pub const startup_logic = struct {
.mode1 = 1, // Use absolute addresses
.base = @intCast((vtable_addr - 4) >> 2),
});

// We set machine mode (0x3) so the user can enable/disable interrupts
// or manage machine/user mode themselves.
// With mpp at 0 the users main function is forced to run at user level.
// Also enable interrupts.
Comment on lines +266 to +269
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I think it would be more clear to explain that mpp = 3 means that the mret will keep us in machine mode.

csr.mstatus.write(.{
.mie = 1,
.mpie = 1,
.fs = if (cpu_name == .@"qingkev4-rv32imafc") .dirty else .off,
.mpp = 0x3,
});

// Initialize the system.
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