From 3082b1cbc0c5de4b018afd9d91cc874d2cb412c8 Mon Sep 17 00:00:00 2001 From: Venkata Ramanaiah Nalamothu Date: Mon, 15 Dec 2025 20:05:17 -0800 Subject: [PATCH 1/9] Schedule information for Xqcia extension instructions --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 748494ffc2935..2c97d93b4cd24 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -472,13 +472,15 @@ class QCIRVInstI funct4, string opcodestr> class QCIRVInstR funct4, string opcodestr> : RVInstR<{0b000, funct4}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd), - (ins GPRNoX0:$rs1), opcodestr, "$rd, $rs1"> { + (ins GPRNoX0:$rs1), opcodestr, "$rd, $rs1">, + Sched<[WriteIALU, ReadIALU]> { let rs2 = 0; } class QCIRVInstRR funct5, DAGOperand InTyRs1, string opcodestr> : RVInstR<{0b00, funct5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd), - (ins InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, "$rd, $rs1, $rs2">; + (ins InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, "$rd, $rs1, $rs2">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; class QCIRVInstRRTied funct5, DAGOperand InTyRs1, string opcodestr> : RVInstR<{0b00, funct5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb), @@ -881,7 +883,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { def QC_WRAP : QCIRVInstRR<0b10010, GPR, "qc.wrap">; def QC_WRAPI : RVInstI<0b000, OPC_CUSTOM_0, (outs GPRNoX0:$rd), (ins GPRNoX0:$rs1, uimm11:$imm11), "qc.wrapi", - "$rd, $rs1, $imm11"> { + "$rd, $rs1, $imm11">, + Sched<[WriteIALU, ReadIALU]> { bits<11> imm11; let imm12 = {0b0, imm11}; From a81d1abd6b2b97f4f4d939207b22bcc419f8d128 Mon Sep 17 00:00:00 2001 From: Venkata Ramanaiah Nalamothu Date: Mon, 15 Dec 2025 20:11:50 -0800 Subject: [PATCH 2/9] Schedule information for Xqciac extension instructions --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 2c97d93b4cd24..d5b20ac0eb59c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -970,7 +970,8 @@ let Predicates = [HasVendorXqciac, IsRV32] in { let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { def QC_C_MULIADD : RVInst16CL<0b001, 0b10, (outs GPRC:$rd_wb), (ins GPRC:$rd, GPRC:$rs1, uimm5:$uimm), - "qc.c.muliadd", "$rd, $rs1, $uimm"> { + "qc.c.muliadd", "$rd, $rs1, $uimm">, + Sched<[WriteIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; bits<5> uimm; @@ -981,13 +982,15 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { def QC_MULIADD : RVInstI<0b110, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, GPRNoX0:$rs1, simm12_lo:$imm12), - "qc.muliadd", "$rd, $rs1, $imm12"> { + "qc.muliadd", "$rd, $rs1, $imm12">, + Sched<[WriteIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; } def QC_SHLADD : RVInstRBase<0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd), (ins GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$shamt), - "qc.shladd", "$rd, $rs1, $rs2, $shamt"> { + "qc.shladd", "$rd, $rs1, $rs2, $shamt">, + Sched<[WriteIALU, ReadIALU, ReadIALU]> { bits<5> shamt; let Inst{31-30} = 0b01; From 9e708f5d0d1baa235df6b7583ab90598570c885d Mon Sep 17 00:00:00 2001 From: Venkata Ramanaiah Nalamothu Date: Mon, 15 Dec 2025 23:41:23 -0800 Subject: [PATCH 3/9] Schedule information for Xqcibm extension instructions --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 26 ++++++++++++++------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index d5b20ac0eb59c..4e1a9329acd01 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -468,7 +468,8 @@ class QCIStore_ScaleIdx funct4, string opcodestr> class QCIRVInstI funct4, string opcodestr> : RVInstIUnary<{0b000, funct4, 0b00000}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd), (ins GPRNoX0:$rs1), opcodestr, - "$rd, $rs1">; + "$rd, $rs1">, + Sched<[WriteIALU, ReadIALU]>; class QCIRVInstR funct4, string opcodestr> : RVInstR<{0b000, funct4}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd), @@ -485,7 +486,8 @@ class QCIRVInstRR funct5, DAGOperand InTyRs1, string opcodestr> class QCIRVInstRRTied funct5, DAGOperand InTyRs1, string opcodestr> : RVInstR<{0b00, funct5}, 0b011, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, InTyRs1:$rs1, GPRNoX0:$rs2), opcodestr, - "$rd, $rs1, $rs2"> { + "$rd, $rs1, $rs2">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; } @@ -493,7 +495,8 @@ class QCIBitManipRII funct3, bits<2> funct2, DAGOperand InTyRs1, string opcodestr> : RVInstIBase { + opcodestr, "$rd, $rs1, $width, $shamt">, + Sched<[WriteIALU, ReadIALU]> { bits<5> shamt; bits<5> width; @@ -506,7 +509,8 @@ class QCIBitManipRIITied funct3, bits<2> funct2, DAGOperand InTyRs1, string opcodestr> : RVInstIBase { + opcodestr, "$rd, $rs1, $width, $shamt">, + Sched<[WriteIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; bits<5> shamt; bits<5> width; @@ -520,7 +524,8 @@ class QCIRVInstRI funct1, DAGOperand InTyImm11, string opcodestr> : RVInstIBase<0b000, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, GPRNoX0:$rs1, InTyImm11:$imm11), opcodestr, - "$rd, $rs1, $imm11"> { + "$rd, $rs1, $imm11">, + Sched<[WriteIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; bits<11> imm11; @@ -918,7 +923,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { def QC_INSBI : RVInstIBase<0b001, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, simm5:$imm5, uimm5_plus1:$width, uimm5:$shamt), "qc.insbi", - "$rd, $imm5, $width, $shamt"> { + "$rd, $imm5, $width, $shamt">, + Sched<[WriteIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; bits<5> imm5; bits<5> shamt; @@ -951,11 +957,13 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { def QC_CLO : QCIRVInstI<0b0100, "qc.clo">; def QC_CTO : QCIRVInstI<0b0101, "qc.cto">; def QC_BREV32 : QCIRVInstI<0b0110, "qc.brev32">; - def QC_C_BEXTI : QCI_RVInst16CB_BM<0b00, "qc.c.bexti">; - def QC_C_BSETI : QCI_RVInst16CB_BM<0b01, "qc.c.bseti">; + def QC_C_BEXTI : QCI_RVInst16CB_BM<0b00, "qc.c.bexti">, + Sched<[WriteIALU, ReadIALU]>; + def QC_C_BSETI : QCI_RVInst16CB_BM<0b01, "qc.c.bseti">, Sched<[WriteIALU]>; def QC_C_EXTU : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, uimm5ge6_plus1:$width), - "qc.c.extu", "$rd, $width"> { + "qc.c.extu", "$rd, $width">, + Sched<[WriteIALU, ReadIALU]> { bits<5> rd; bits<5> width; let Constraints = "$rd = $rd_wb"; From 42144ba94845bfca4d70f630448926d8d9e8b29c Mon Sep 17 00:00:00 2001 From: Venkata Ramanaiah Nalamothu Date: Tue, 16 Dec 2025 02:00:41 -0800 Subject: [PATCH 4/9] Schedule information for Xqcicli extension instructions --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 38 ++++++++++++++------- 1 file changed, 25 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 4e1a9329acd01..46e14dc28ee04 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -1030,19 +1030,31 @@ let Predicates = [HasVendorXqcilsm, IsRV32] in { } // Predicates = [HasVendorXqcilsm, IsRV32] let Predicates = [HasVendorXqcicli, IsRV32] in { - def QC_LIEQ : QCILICC<0b000, 0b01, GPRNoX0, "qc.lieq">; - def QC_LINE : QCILICC<0b001, 0b01, GPRNoX0, "qc.line">; - def QC_LILT : QCILICC<0b100, 0b01, GPRNoX0, "qc.lilt">; - def QC_LIGE : QCILICC<0b101, 0b01, GPRNoX0, "qc.lige">; - def QC_LILTU : QCILICC<0b110, 0b01, GPRNoX0, "qc.liltu">; - def QC_LIGEU : QCILICC<0b111, 0b01, GPRNoX0, "qc.ligeu">; - - def QC_LIEQI : QCILICC<0b000, 0b11, simm5, "qc.lieqi">; - def QC_LINEI : QCILICC<0b001, 0b11, simm5, "qc.linei">; - def QC_LILTI : QCILICC<0b100, 0b11, simm5, "qc.lilti">; - def QC_LIGEI : QCILICC<0b101, 0b11, simm5, "qc.ligei">; - def QC_LILTUI : QCILICC<0b110, 0b11, uimm5, "qc.liltui">; - def QC_LIGEUI : QCILICC<0b111, 0b11, uimm5, "qc.ligeui">; + def QC_LIEQ : QCILICC<0b000, 0b01, GPRNoX0, "qc.lieq">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_LINE : QCILICC<0b001, 0b01, GPRNoX0, "qc.line">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_LILT : QCILICC<0b100, 0b01, GPRNoX0, "qc.lilt">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_LIGE : QCILICC<0b101, 0b01, GPRNoX0, "qc.lige">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_LILTU : QCILICC<0b110, 0b01, GPRNoX0, "qc.liltu">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_LIGEU : QCILICC<0b111, 0b01, GPRNoX0, "qc.ligeu">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + + def QC_LIEQI : QCILICC<0b000, 0b11, simm5, "qc.lieqi">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_LINEI : QCILICC<0b001, 0b11, simm5, "qc.linei">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_LILTI : QCILICC<0b100, 0b11, simm5, "qc.lilti">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_LIGEI : QCILICC<0b101, 0b11, simm5, "qc.ligei">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_LILTUI : QCILICC<0b110, 0b11, uimm5, "qc.liltui">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_LIGEUI : QCILICC<0b111, 0b11, uimm5, "qc.ligeui">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; } // Predicates = [HasVendorXqcicli, IsRV32] let Predicates = [HasVendorXqcicm, IsRV32] in { From b0fa4437a64cec90fe81c7f958dcf80caf90c62d Mon Sep 17 00:00:00 2001 From: Venkata Ramanaiah Nalamothu Date: Tue, 16 Dec 2025 02:11:38 -0800 Subject: [PATCH 5/9] Schedule information for Xqcicm extension instructions --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 41 ++++++++++++++------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 46e14dc28ee04..6680c77633ed0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -1061,26 +1061,39 @@ let Predicates = [HasVendorXqcicm, IsRV32] in { let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in def QC_C_MVEQZ : RVInst16CL<0b101, 0b10, (outs GPRC:$rd_wb), (ins GPRC:$rd, GPRC:$rs1), - "qc.c.mveqz", "$rd, $rs1"> { + "qc.c.mveqz", "$rd, $rs1">, + Sched<[WriteIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; let Inst{12-10} = 0b011; let Inst{6-5} = 0b00; } - def QC_MVEQ : QCIMVCC<0b000, "qc.mveq">; - def QC_MVNE : QCIMVCC<0b001, "qc.mvne">; - def QC_MVLT : QCIMVCC<0b100, "qc.mvlt">; - def QC_MVGE : QCIMVCC<0b101, "qc.mvge">; - def QC_MVLTU : QCIMVCC<0b110, "qc.mvltu">; - def QC_MVGEU : QCIMVCC<0b111, "qc.mvgeu">; - - def QC_MVEQI : QCIMVCCI<0b000, "qc.mveqi", simm5>; - def QC_MVNEI : QCIMVCCI<0b001, "qc.mvnei", simm5>; - def QC_MVLTI : QCIMVCCI<0b100, "qc.mvlti", simm5>; - def QC_MVGEI : QCIMVCCI<0b101, "qc.mvgei", simm5>; - def QC_MVLTUI : QCIMVCCI<0b110, "qc.mvltui", uimm5>; - def QC_MVGEUI : QCIMVCCI<0b111, "qc.mvgeui", uimm5>; + def QC_MVEQ : QCIMVCC<0b000, "qc.mveq">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_MVNE : QCIMVCC<0b001, "qc.mvne">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_MVLT : QCIMVCC<0b100, "qc.mvlt">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_MVGE : QCIMVCC<0b101, "qc.mvge">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_MVLTU : QCIMVCC<0b110, "qc.mvltu">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_MVGEU : QCIMVCC<0b111, "qc.mvgeu">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + + def QC_MVEQI : QCIMVCCI<0b000, "qc.mveqi", simm5>, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_MVNEI : QCIMVCCI<0b001, "qc.mvnei", simm5>, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_MVLTI : QCIMVCCI<0b100, "qc.mvlti", simm5>, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_MVGEI : QCIMVCCI<0b101, "qc.mvgei", simm5>, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_MVLTUI : QCIMVCCI<0b110, "qc.mvltui", uimm5>, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_MVGEUI : QCIMVCCI<0b111, "qc.mvgeui", uimm5>, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; } // Predicates = [HasVendorXqcicm, IsRV32] let Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1 in { From 8777c0f04ceb3dc79bb8fc64ae1d6865f3a61fe8 Mon Sep 17 00:00:00 2001 From: Venkata Ramanaiah Nalamothu Date: Tue, 16 Dec 2025 02:31:00 -0800 Subject: [PATCH 6/9] Schedule information for Xqcics extension instructions --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 24 ++++++++++++++------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 6680c77633ed0..411ace89dba4a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -1009,14 +1009,22 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { } // Predicates = [HasVendorXqciac, IsRV32] let Predicates = [HasVendorXqcics, IsRV32] in { - def QC_SELECTIIEQ : QCISELECTIICC <0b010, "qc.selectiieq">; - def QC_SELECTIINE : QCISELECTIICC <0b011, "qc.selectiine">; - def QC_SELECTIEQ : QCISELECTICC <0b010, "qc.selectieq">; - def QC_SELECTINE : QCISELECTICC <0b011, "qc.selectine">; - def QC_SELECTEQI : QCISELECTCCI <0b010, "qc.selecteqi">; - def QC_SELECTNEI : QCISELECTCCI <0b011, "qc.selectnei">; - def QC_SELECTIEQI : QCISELECTICCI <0b010, "qc.selectieqi">; - def QC_SELECTINEI : QCISELECTICCI <0b011, "qc.selectinei">; + def QC_SELECTIIEQ : QCISELECTIICC <0b010, "qc.selectiieq">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_SELECTIINE : QCISELECTIICC <0b011, "qc.selectiine">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_SELECTIEQ : QCISELECTICC <0b010, "qc.selectieq">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_SELECTINE : QCISELECTICC <0b011, "qc.selectine">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_SELECTEQI : QCISELECTCCI <0b010, "qc.selecteqi">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_SELECTNEI : QCISELECTCCI <0b011, "qc.selectnei">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; + def QC_SELECTIEQI : QCISELECTICCI <0b010, "qc.selectieqi">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_SELECTINEI : QCISELECTICCI <0b011, "qc.selectinei">, + Sched<[WriteIALU, ReadIALU, ReadIALU]>; } // Predicates = [HasVendorXqcics, IsRV32] let Predicates = [HasVendorXqcilsm, IsRV32] in { From 4029e0aae692fb21c734ca83a88fe0e1814bee2e Mon Sep 17 00:00:00 2001 From: Venkata Ramanaiah Nalamothu Date: Tue, 16 Dec 2025 04:49:56 -0800 Subject: [PATCH 7/9] Schedule information for Xqcili extension instructions --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 411ace89dba4a..ea97600b12d8c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -1190,14 +1190,15 @@ let Predicates = [HasVendorXqcilb, IsRV32] in { let Predicates = [HasVendorXqcili, IsRV32] in { let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { def QC_LI : RVInstU { + "qc.li", "$rd, $imm20">, Sched<[WriteIALU]> { let Inst{31} = imm20{19}; let Inst{30-16} = imm20{14-0}; let Inst{15-12} = imm20{18-15}; } def QC_E_LI : RVInst48<(outs GPRNoX0:$rd), (ins bare_simm32:$imm), - "qc.e.li", "$rd, $imm", [], InstFormatQC_EAI> { + "qc.e.li", "$rd, $imm", [], InstFormatQC_EAI>, + Sched<[WriteIALU]> { bits<5> rd; bits<32> imm; From b3dd5613b82663217363806477a7d6b26f89bab9 Mon Sep 17 00:00:00 2001 From: Venkata Ramanaiah Nalamothu Date: Tue, 16 Dec 2025 05:03:26 -0800 Subject: [PATCH 8/9] Schedule information for Xqcilia extension instructions --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index ea97600b12d8c..78eacc6f825cb 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -789,7 +789,8 @@ class QCIRVInstESStore funct3, bits<2> funct2, string opcodestr> class QCIRVInstEAI funct3, bits<1> funct1, string opcodestr> : RVInst48<(outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, bare_simm32:$imm), - opcodestr, "$rd, $imm", [], InstFormatOther> { + opcodestr, "$rd, $imm", [], InstFormatOther>, + Sched<[WriteIALU, ReadIALU]> { bits<5> rd; bits<32> imm; @@ -804,7 +805,8 @@ class QCIRVInstEAI funct3, bits<1> funct1, string opcodestr> class QCIRVInstEI funct3, bits<2> funct2, string opcodestr> : QCIRVInstEIBase; + "$rd, $rs1, $imm">, + Sched<[WriteIALU, ReadIALU]>; let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class QCIRVInst48EJ func2, string opcodestr> From fe70c4e847b058954169b2f76ac33112cd13e476 Mon Sep 17 00:00:00 2001 From: Venkata Ramanaiah Nalamothu Date: Wed, 17 Dec 2025 00:53:12 -0800 Subject: [PATCH 9/9] Address review comments --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 83 +++++++++------------ 1 file changed, 35 insertions(+), 48 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 78eacc6f825cb..c1fb5a7ebfd4b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -537,7 +537,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in class QCISELECTIICC funct3, string opcodestr> : RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2), - opcodestr, "$rd, $rs1, $simm1, $simm2"> { + opcodestr, "$rd, $rs1, $simm1, $simm2">, + Sched<[WriteIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; bits<5> simm1; bits<5> simm2; @@ -550,7 +551,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in class QCISELECTICC funct3, string opcodestr> : RVInstR4<0b01, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2), - opcodestr, "$rd, $rs1, $rs2, $simm2"> { + opcodestr, "$rd, $rs1, $rs2, $simm2">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; bits<5> simm2; @@ -561,7 +563,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class QCISELECTCCI funct3, string opcodestr> : RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, GPRNoX0:$rs3), - opcodestr, "$rd, $imm, $rs2, $rs3"> { + opcodestr, "$rd, $imm, $rs2, $rs3">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; bits<5> imm; @@ -572,7 +575,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class QCISELECTICCI funct3, string opcodestr> : RVInstR4<0b11, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2), - opcodestr, "$rd, $imm, $rs2, $simm2"> { + opcodestr, "$rd, $imm, $rs2, $simm2">, + Sched<[WriteIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; bits<5> imm; bits<5> simm2; @@ -617,7 +621,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in class QCIMVCC funct3, string opcodestr> : RVInstR4<0b00, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, GPRNoX0:$rs3), - opcodestr, "$rd, $rs1, $rs2, $rs3"> { + opcodestr, "$rd, $rs1, $rs2, $rs3">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU, ReadIALU]> { let Constraints = "$rd = $rd_wb"; } @@ -625,7 +630,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCommutable = 1 in class QCIMVCCI funct3, string opcodestr, DAGOperand immType> : RVInstR4<0b10, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, GPRNoX0:$rs1, immType:$imm, GPRNoX0:$rs3), - opcodestr, "$rd, $rs1, $imm, $rs3"> { + opcodestr, "$rd, $rs1, $imm, $rs3">, + Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]> { bits<5> imm; let Constraints = "$rd = $rd_wb"; @@ -961,7 +967,8 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { def QC_BREV32 : QCIRVInstI<0b0110, "qc.brev32">; def QC_C_BEXTI : QCI_RVInst16CB_BM<0b00, "qc.c.bexti">, Sched<[WriteIALU, ReadIALU]>; - def QC_C_BSETI : QCI_RVInst16CB_BM<0b01, "qc.c.bseti">, Sched<[WriteIALU]>; + def QC_C_BSETI : QCI_RVInst16CB_BM<0b01, "qc.c.bseti">, + Sched<[WriteIALU, ReadIALU]>; def QC_C_EXTU : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb), (ins GPRNoX0:$rd, uimm5ge6_plus1:$width), "qc.c.extu", "$rd, $width">, @@ -1011,22 +1018,14 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { } // Predicates = [HasVendorXqciac, IsRV32] let Predicates = [HasVendorXqcics, IsRV32] in { - def QC_SELECTIIEQ : QCISELECTIICC <0b010, "qc.selectiieq">, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; - def QC_SELECTIINE : QCISELECTIICC <0b011, "qc.selectiine">, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; - def QC_SELECTIEQ : QCISELECTICC <0b010, "qc.selectieq">, - Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; - def QC_SELECTINE : QCISELECTICC <0b011, "qc.selectine">, - Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; - def QC_SELECTEQI : QCISELECTCCI <0b010, "qc.selecteqi">, - Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; - def QC_SELECTNEI : QCISELECTCCI <0b011, "qc.selectnei">, - Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; - def QC_SELECTIEQI : QCISELECTICCI <0b010, "qc.selectieqi">, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; - def QC_SELECTINEI : QCISELECTICCI <0b011, "qc.selectinei">, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_SELECTIIEQ : QCISELECTIICC <0b010, "qc.selectiieq">; + def QC_SELECTIINE : QCISELECTIICC <0b011, "qc.selectiine">; + def QC_SELECTIEQ : QCISELECTICC <0b010, "qc.selectieq">; + def QC_SELECTINE : QCISELECTICC <0b011, "qc.selectine">; + def QC_SELECTEQI : QCISELECTCCI <0b010, "qc.selecteqi">; + def QC_SELECTNEI : QCISELECTCCI <0b011, "qc.selectnei">; + def QC_SELECTIEQI : QCISELECTICCI <0b010, "qc.selectieqi">; + def QC_SELECTINEI : QCISELECTICCI <0b011, "qc.selectinei">; } // Predicates = [HasVendorXqcics, IsRV32] let Predicates = [HasVendorXqcilsm, IsRV32] in { @@ -1079,31 +1078,19 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in let Inst{6-5} = 0b00; } - def QC_MVEQ : QCIMVCC<0b000, "qc.mveq">, - Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; - def QC_MVNE : QCIMVCC<0b001, "qc.mvne">, - Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; - def QC_MVLT : QCIMVCC<0b100, "qc.mvlt">, - Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; - def QC_MVGE : QCIMVCC<0b101, "qc.mvge">, - Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; - def QC_MVLTU : QCIMVCC<0b110, "qc.mvltu">, - Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; - def QC_MVGEU : QCIMVCC<0b111, "qc.mvgeu">, - Sched<[WriteIALU, ReadIALU, ReadIALU, ReadIALU]>; - - def QC_MVEQI : QCIMVCCI<0b000, "qc.mveqi", simm5>, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; - def QC_MVNEI : QCIMVCCI<0b001, "qc.mvnei", simm5>, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; - def QC_MVLTI : QCIMVCCI<0b100, "qc.mvlti", simm5>, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; - def QC_MVGEI : QCIMVCCI<0b101, "qc.mvgei", simm5>, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; - def QC_MVLTUI : QCIMVCCI<0b110, "qc.mvltui", uimm5>, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; - def QC_MVGEUI : QCIMVCCI<0b111, "qc.mvgeui", uimm5>, - Sched<[WriteIALU, ReadIALU, ReadIALU]>; + def QC_MVEQ : QCIMVCC<0b000, "qc.mveq">; + def QC_MVNE : QCIMVCC<0b001, "qc.mvne">; + def QC_MVLT : QCIMVCC<0b100, "qc.mvlt">; + def QC_MVGE : QCIMVCC<0b101, "qc.mvge">; + def QC_MVLTU : QCIMVCC<0b110, "qc.mvltu">; + def QC_MVGEU : QCIMVCC<0b111, "qc.mvgeu">; + + def QC_MVEQI : QCIMVCCI<0b000, "qc.mveqi", simm5>; + def QC_MVNEI : QCIMVCCI<0b001, "qc.mvnei", simm5>; + def QC_MVLTI : QCIMVCCI<0b100, "qc.mvlti", simm5>; + def QC_MVGEI : QCIMVCCI<0b101, "qc.mvgei", simm5>; + def QC_MVLTUI : QCIMVCCI<0b110, "qc.mvltui", uimm5>; + def QC_MVGEUI : QCIMVCCI<0b111, "qc.mvgeui", uimm5>; } // Predicates = [HasVendorXqcicm, IsRV32] let Predicates = [HasVendorXqciint, IsRV32], hasSideEffects = 1 in {