Fewer Assigns of Constants in ExportVerilog (#3106)

Fold assignments of constants to wires into the wire declaration.

Author: darthscsi

lib/Conversion/ExportVerilog/ExportVerilog.cpp

@@ -2270,17 +2270,22 @@ SubExprInfo ExprEmitter::visitUnhandledExpr(Operation *op) {
 // NameCollector
 //===----------------------------------------------------------------------===//
 
-
-static ConstantOp isSingleConstantAssign(Operation *op) {
+static std::pair<ConstantOp, AssignOp> isSingleConstantAssign(Operation *op) {
   auto wire = dyn_cast<WireOp>(op);
   if (!wire)
     return {};
-  if (!wire->hasOneUse())
-    return {};
-  auto assign = dyn_cast<AssignOp>(*wire->user_begin());
-  if (!assign)
+  ConstantOp con;
+  AssignOp assignOp;
+  for (auto *user : wire->getUsers()) {
+    auto assign = dyn_cast<AssignOp>(*user);
+    if (assign && assignOp)
+      return {};
+    assignOp = assign;
+  }
+  if (!assignOp)
     return {};
-  return dyn_cast_or_null<ConstantOp>(assign->getOperand(1).getDefiningOp());
+  return std::make_pair(
+      dyn_cast_or_null<ConstantOp>(assignOp.src().getDefiningOp()), assignOp);
 }
 
 namespace {
@@ -3695,10 +3700,11 @@ void StmtEmitter::collectNamesEmitDecls(Block &block) {
       emitter.expressionsEmittedIntoDecl.insert(op);
     }
 
-    if (auto constOp = isSingleConstantAssign(op)) {
+    auto [constOp, assignOp] = isSingleConstantAssign(op);
+    if (constOp) {
       os << " = ";
       emitExpression(constOp, opsForLocation, ForceEmitMultiUse);
-      emitter.assignsInlined.insert(*op->user_begin());
+      emitter.assignsInlined.insert(assignOp);
     }
 
     os << ';';

test/Conversion/ExportVerilog/verilog-basic.mlir

@@ -298,6 +298,20 @@ hw.module @MultiUseExpr(%a: i4) -> (b0: i1, b1: i1, b2: i1, b3: i1, b4: i2) {
   hw.output %0, %3, %4, %5, %7 : i1, i1, i1, i1, i2
 }
 
+// CHECK-LABEL: module SimpleConstPrint(
+// CHECK-NEXT:    input  [3:0] in4,
+// CHECK-NEXT:    output [3:0] out4);
+// CHECK:  wire [3:0] w = 4'h1;
+// CHECK:  assign out4 = in4 + w;
+// CHECK-NEXT: endmodule
+hw.module @SimpleConstPrint(%in4: i4) -> (out4: i4) {
+  %w = sv.wire : !hw.inout<i4>
+  %c1_i4 = hw.constant 1 : i4
+  sv.assign %w, %c1_i4 : i4
+  %1 = comb.add %in4, %c1_i4 : i4
+  hw.output %1 : i4
+}
+
 hw.module.extern @MyExtModule(%in: i8) -> (out: i1) attributes {verilogName = "FooExtModule"}
 hw.module.extern @AParameterizedExtModule<CFG: none>(%in: i8) -> (out: i1)